AGC CIRCUIT
 
A portion of the output from the AM detector is fed to DC amplifiers Q1028 and Q1029 (2SC945A-Q). This amplified DC voltage is applied to gate of the RF and IF amplifiers, controlling the gain of those stages.
 
MUTE CIRCUIT
 
Q1035 is normally in the "ON" state, providing normal bias voltage to gate 1 Of Q1014 and Q1024 When the MUTE terminal is shorted to ground, Q1035 turns off, removing the bias voltage from the above transistors, thus silencing the receiver.
 
CLOCK AND DIGITAL DISPLAY CIRCUIT
 
A Large Scale Integration (LSI) chip, Q1046 (MSM5524), controls both the display of the operating frequency and the time. An 0.455 - 30.455 MHz signal from the PLL Unit is amplified by Q1041 , Q1042, and Q1043 (2SC1674L), then fed through divider (1/10) Q1044 (SN74LS196) to the LSI chip. The output from Q1046 is fed to the fluourescent display tube, (DS1001), through segment drivers Q1052 - Q1058 (2SA733A-Q). Q1060 and Q1061act as a DC-DC converter, providing -25 volts DC for the display tube.
 
The timer control output from the LSI activates relay RL1001 , which controls the receiver main power supply ON/OFF function. RL1001 also is connected to the REMOTE terminals on the rear panel of the receiver, for control of peripheral station equipment.
 
PLL CIRCUIT
 
The first and second local signals (48.055 - 78.055 MHz and 47.6 MHz, respectively) are generated by the dual loop PLL (Phase Locked Loop) circuit.
 
A 44.055 - 45.055 MHz signal is generated by VCO (Voltage Controlled Oscillator) Q2028 (2SC945A-Q) in PLL Loop 1. This signal feeds mixer Q2030 (SN16913P), where the VCO signal is mixed with a 47.6 MHz signal generated by crystal ocilator Q2016 (2SC535A). producing a 3.545 -
 
2.545 MHz signal which is fed to phase detector Q2025 (MC4044P). The phase detector compares the phase of the input signal with that of the VFO signal delivered via Q2024 (2SC94SA-Q): any phase difference is converted to a DC control voltage. which is fed to varactor diodes in the VCO circuit, in order to correct the phase difference and lock the input signal with the VFO signal.
 
In PLL Loop 2, there are four VCO circuits which are selected by the bandswitch, with the net result being an output signal of 48.055 - 78.055 MHz. This signal is fed to mixer Q2033 (SN16913P), where the input signal is mixed with the 44.055 - 45.055 MHz signal delivered from PLL Loop 1, producing a 4 - 33 MHz signal. This signal is fed through divider ( l/10) Q2036 (HD10551P) to phase detector Q2042 (MB8718), which also contains a programmable divider.
 
Phase detector Q2042 compares the phase of the signal from the onboard programmable divider and that of the 100 kHz reference signal generated by Q2039, Q2040 (2SC945A Q), and Q2041 (MB84040), producing an error-correcting DC voltage. The dividing ratio of the programmable divider is selected by the bandswitch. The error correction voltage is fed to varactor diodes in VCO/1 - VCO/4, thus locking a highly stable 48.055 - 78.055 MHz signal, which will be used as the first local signal. The VCO output is fed through buffers Q2012 (2SC1047C) and Q2013 (2SC1959Y) prior to delivery to the first mixer.
 
The second local signal (47.6 MHz) is generated by Q2016, then amplified by Q2017 (2SC1393L) and fed through buffer Q2021 (2SC945A-Q) prior to delivery to the second mixer.
 
A portion of the first local signal is fed to mixer Q2019 (SN16913P), where the signal is mixed with the 47.6 MHz second local signal. producing a signal at 0.455 - 30.455 MHz which is fed to the LSl chip in the counter for display of the operating frequency.