CIRCUIT DESCRIPTION

The block diagram will provide you with a better understanding of this receiver. In general, the FRG-7 is a tripple conversion super heterodyne receiver utilizing synthesized local oscillator for both the first and second mixers for drift free VFO operation.


The signal from the antenna is fed through the attenuator to the gate of the FET RF amplifier Q101, 3SK40. The amplified signal is fed through a low pass filter (cut off frequency 35 MHz) to the first balanced mixer consisting of Q102 and Q103, 2SK19, where the incoming signal is mixed with a signal from the heterodyne oscillator. The first heterodyne oscillator Q201 2SC784, oscillates the signal which varies between 55.5 and 84.5 MHz.


The product of the first mixer becomes the first IF signal of 54.5 through 55.5 MHz. The first IF signal is amplified by the first IF passband ampli fier Q104 and fed to the gate of the second mixer Q105, 2SK19CR, where the first IF signal is mixed with 52.5 MHz signal. The second mixer converts the first IF signal into the second IF signal of 2.0 through 3.0 MHz.


Synthesizer oscillator Q301 2SC372, oscillates crystal controlled 1 MHz signal. The 1 MHz signal is then fed to the harmonic generator D301 and D302, 1N60, which produces 3 to 32 MHz harmonics from the 1 MHz crystal controlled signal. The harmonic signal is fed to the dual balanced pre-mixer Q106, SN76514, where the harmonics are mixed with the signal from the first heterodyne oscillator Q201. The output signal from the pre-mixer passes through the selective amplifier Q107, Q108 and Q109, 2SC784, which eliminates other signals except the 52.5 MHz second heterodyne signal.


A part of the output from the selective amplifier is rectified by the detectors D1 and D2 , 1S1555, and the DC output voltage is amplified by the DC amplifier Q110, 2SC372, and then fed to the LOCK lamp driver Q111, 2SC372, which turns the LOCK lamp on when the synthesizer is unlocked.


The output signal from the first IF amplifier Q104 is fed to the second mixer Q105, 2SK 19, where the

incoming signal is mixed with the 52.5 Mhz signal from the selective amplifier. The output of the second mixer becomes second IF signal of 2.0 through 3.0 MHz. The 2.0 to 3.0 MHz IF signal is then amplified by the second IF amplifier Q401 3SK40, and then fed to the third mixer Q4o2 2SK19. The third mixer converts the second IF signal into 455 kHz third IF signal. The VFO (main tuning) signal, which varies between 2,455 kHz and 3,455 kHz, is generated by the variable frequency oscillator Q403, 2SC372. and supplied to the third mixer through the buffer amplifier Q404, 2SK19. The 455 kHz IF signal from the third mixer is fed to the ceramic filter which is tuned to 455 kHz and has ±3 kHz passband response to eliminate interference.


The signal is then amplified by the third amplifier Q405 and Q406, 2SC372, and fed to the appropriate detector. The AM signal is detected by balanced diode detector D402, 1N6OAM.


The balanced demodulator D403 through D406, IN6OAM, is used for the detection of SSB and CW signals. The carrier signal for SSB and the beat frequency signal for CW which is generated by the BFO oscillator Q408, 2SK19, are fed to the balanced demodulator through buffer amplifier, Q409 , 2SC372. The MODE switch shifts the BFO frequency 3 kHz lower than LSB position for USB and CW signal reception.


A part of the output from the last IF amplifier Q406 is fed to the AGC (Automatic Gain Control) rectifier D401 , 1N60. The rectified AGC voltage is then amplified by the AGC amplifier Q407, 2SC372, and fed to the Q101, Q401 and Q405 to control the gain of these stages automatically when the incoming signal strength is varied. Thus the receiver audio output is not effected by the varia tion of the input signal strength which may be caused by phasing. The S-meter is placed in the emitter circuit of Q407in which the emitter current changes in accordance with the incoming signal strength.


The detected audio output is fed through the MODE switch and the VOLUME control potentiometer VR1 to the audio amplifier integrated circuit



Return to FRG-7 Index Updated 21 June, 2001 Maintained by Kent Walker